This application is based upon and claims priority of Japanese Patent Applications No.2001-114009, filed in Apr. 12, 2001, the contents being incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor device having a capacitor constituted by stacking a lower capacitor electrode, an insulating film and an upper capacitor electrode, and a manufacturing method of the same. More specifically, the present invention relates to a semiconductor device including a silicide film in its wiring connection portion and a manufacturing method of the same.
2. Description of the Prior Art
Recently, high integration and microfabrication of semiconductor devices have been promoted, and electrode of low resistivity has been required accompanied with the promotions of them. In order to realize low resistivity of electrodes, a process of reacting silicon with metallic atoms of titanium (Ti), cobalt (Co) and the like, called a silicide process is utilized.
FIG. 1 is a sectional view of a conventional semiconductor device including a metal oxide semiconductor (hereinafter referred to as xe2x80x9cMOSxe2x80x9d) transistor 71 with a lightly doped drain (hereinafter referred to as xe2x80x9cLDDxe2x80x9d) structure and a stacked capacitor 72.
A manufacturing method of the conventional semiconductor device will be described with reference to FIG. 1.
First, an electrically insulative element isolation film 52 is formed on a silicon substrate 51. Thereafter, a gate insulating film 53 is formed on a transistor forming region of the silicon substrate 51.
Next, on the entire surface of the silicon substrate 51, a first polysilicon film is formed. The first polysilicon film serves as a gate electrode 54 and a lower capacitor electrode 55. On the lower capacitor electrode 55, formed are an oxide film serving as a capacitor insulating film 56 and a second polysilicon film serving as an upper capacitor electrode 57.
Thereafter, the second polysilicon film and the oxide film are respectively subjected to patterning, thus forming the upper capacitor electrode 57 and the capacitor insulating film 56. Subsequently, the first polysilicon film is subjected to patterning, thus forming the gate electrode 54 and the lower capacitor electrode 55. Thereafter, impurities are ion-implanted onto a surface of the silicon substrate 51 at a low concentration using the gate electrode 54 as a mask, thus forming a low-concentration impurity region (i.e., an LDD region) 58 in a self-aligned manner with the gate electrode 54.
Next, a silicon oxide film is formed on the entire surface of the resultant structure. Then, the silicon oxide film is subjected to anisotropic etching so that the silicon oxide film remains only on side portions of: the gate electrode 54; the lower capacitor electrode 55; and the upper capacitor electrode 57. In this way, sidewalls 59a, 59b and 59c made of silicon oxide films are formed, which cover the side portions of the gate electrode 54, the lower capacitor electrode 55 and the upper capacitor electrode 57, respectively.
Next, impurities are ion-implanted onto the surface of the silicon substrate 51 at a high concentration using the gate electrode 54 and the sidewall 59a as a mask, thus forming a high-concentration impurity region (a source/drain region) 60 in a self-aligned manner with the gate electrode 54 and the sidewall 59a. 
Next, the entire surface of the resultant structure is subjected to sputtering either with Ti or Co, thus forming a metallic film. Thereafter, the substrate is subjected to annealing (a heating process) and either Ti or Co atoms contained in the metallic film react with silicon atoms contained in the gate electrode 54, the high-concentration impurity region 60, the lower capacitor electrode 55 and the upper capacitor electrode 57. Thus silicide films 61a, 61b, 61c and 61d are formed. Thereafter, the metallic film is removed.
In this way, a MOS transistor 71 of LDD structure and a stacked capacitor 72 are formed as shown in FIG. 1. Thereafter, an interlayer insulating film (not illustrated) and a wiring (not illustrated) are formed, and a desired circuit is thereby formed.
The inventors of the present invention perceive that the above-described manufacturing method of a semiconductor device has a problem as follows.
In recent years, along with the progress of high integration and microfabrication of semiconductor devices, thinning of films of the capacitor electrode (particularly for the upper capacitor electrode 57) has been required. However, when the films of the capacitor are thinned, or when metallic films for silicide formation are thickened or an annealing temperature is raised for ensuring a reaction of silicon and metallic atoms, the silicide film 61c on the lower capacitor electrode 55 extends upward along a side face of the sidewall 59c (xe2x80x9ccreeping-upxe2x80x9d), or the silicide film 61d on the upper capacitor electrode 57 extends downward along a side face of the sidewall 59c (xe2x80x9ccreeping-downxe2x80x9d). Such a problem may incur a short circuit or a current leakage.
An object of the present invention is to provide a semiconductor device having a capacitor, and a manufacturing method of the same, capable of preventing a short circuit and a current leakage incurred by silicide of a sidewall portion on a side of a capacitor electrode.
In order to achieve the above-mentioned object, a semiconductor device of the present invention comprises: a semiconductor substrate; an insulating film formed on the semiconductor substrate; a lower capacitor electrode formed on the insulating film; a first sidewall made of an insulating material covering a side face of the lower capacitor electrode; a capacitor insulating film formed on the lower capacitor electrode; an upper capacitor electrode formed on the capacitor insulating film; a second sidewall made of an insulating material covering a side face and an upper periphery of the upper capacitor electrode; a first silicide film formed on a portion of the lower capacitor electrode where the portion is not covered with the capacitor insulating film; and a second silicide film formed on a portion of the upper capacitor electrode where the portion is not covered with the second sidewall.
With the above-described constitution, in the semiconductor device of the present invention, since a sidewall is formed so as to cover not only the side portion of the upper capacitor electrode but also the upper periphery thereof, a distance between the silicide film on the surface of the lower capacitor electrode and the silicide film on the surface of the upper capacitor electrode (a distance along the surface of the sidewall) is made large. Accordingly, a contact of a creeping-up portion of the silicide from the lower capacitor electrode side and with a creeping-down portion of the silicide from the upper capacitor electrode side is prevented even in a case where a thickness of the upper capacitor electrode is made as thin as 80 to 180 nm. Thus, occurrence of a defect such as a short circuit or a current leakage is avoided.
Also, a manufacturing method of a semiconductor device according to the present invention comprises the steps of: forming an insulative element isolation film on a semiconductor substrate; forming a first silicon film on the entire surface of the semiconductor substrate; forming a first insulating film on the first silicon film; forming a second silicon film on the first insulating film; forming a capacitor insulating film and an upper capacitor electrode above an upper side of the element isolation film by patterning the first insulating film and the second silicon film; forming a first resist film including a first pattern that covers the upper capacitor electrode and the capacitor insulating film, and a second pattern that covers a gate electrode formation region; forming a lower capacitor electrode and a gate electrode by patterning the first silicon film by use of the first resist film as a mask; introducing first impurities onto a surface layer of the semiconductor substrate at both side portions of the gate electrode after removing the first resist film; forming a second insulating film on the entire surface of the resultant structure; forming a second resist film on the second insulating film, the second resist film covering a region extending from the inside of a periphery of the upper capacitor electrode to the outside of the periphery thereof; anisotropically etching the second insulating film to form sidewalls on a side portion of the gate electrode, a side portion of the lower capacitor electrode and a bottom portion of the second resist film, respectively; removing the second resist film; introducing second impurities onto the semiconductor substrate using the gate electrode and the sidewalls on the both sides thereof collectively as a mask; forming a metallic film on the entire surface of the resultant structure and further allowing metallic atoms in the metallic film to react with silicon contained in the semiconductor substrate, the gate electrode, the lower capacitor electrode and the upper capacitor electrode, thus forming a silicide film; and removing the metallic film while leaving the silicide film.
With the above-described constitution, in the manufacturing method of the present invention, the resist film is formed on the second insulating film, the resist film covering a region extending from the inside of the periphery of the upper capacitor electrode to the outside of the periphery thereof. Thus, the insulating film partially remains under the resist film when anisotropic etching is performed for the insulating film, and the remaining part thereof forms a sidewall on the upper capacitor electrode side.
Therefore, a side wall is formed so as to cover not only the side portion of the upper capacitor electrode but also the upper periphery thereof. As a result, a contact of a creeping-up portion of the silicide from the lower capacitor electrode side and with a creeping-down portion of the silicide from the upper capacitor electrode side is prevented. Thus, occurrence of a defect such as a short circuit or a current leakage is avoided.